Starting with the 0.35 μm generation, CMOS scaling has changed from a constant-voltage regime with a nominal supply voltage of 5V to a constant-field regime where the supply voltage is being reduced in concert with geometric dimensions with each process generation. We are thus likely to see more and more CMOS circuits in the future that must operate with a supply voltage below that of the usual sources of electrical energy. As an example, consider a 1.2V battery cell that feeds a low-power low-voltage circuit operating at a mere 0.6V. The most obvious solution is to use a voltage converter in down mode. While this is possible, the converter is costly, space consuming, and also has its own power dissipation. Partitioning the overall IC into two or more sub-circuits and connecting them in series does away with the down converter because the IC can so be powered from a supply with a higher voltage than what is suitable for an individual sub-circuit. U.S. Pat. No. 6,479,974 further proposes to adjust the voltages across the various sub-circuits with the aid of controllable current sources that bleed off excess voltage. The invention improves on the energy-efficiency and on the simplicity of series-connected power schemes by doing the voltage balancing with capacitor switching instead.
According to U.S. Pat. No. 6,479,974, the circuit on the IC is partitioned into power-consuming sub-circuits each of which is to be fed with its own supply voltage and the sub-circuits are then connected in series. This effectively cuts the supply voltage for each sub-circuit. In this way it becomes possible to use a battery cell with a high voltage to feed a low voltage circuit without the need to provide the usual down converter. As voltage drops across the individual sub-circuits will tend to distribute unevenly because current drains in the various workload sub-circuits are never quite the same, U.S. Pat. No. 6,479,974 proposes to compensate for this undesirable effect by connecting a regulator in parallel with each sub-circuit. A controlled current source in each regulator adjusts its current drain such as to maintain a fixed voltage across its own terminals and, hence, across the power-consuming sub-circuit as well. An extra central unit is utilized to coordinate the various regulators such that at least one of them draws zero current thereby minimizing the collective current drain from the power supply.
An alternative embodiment of U.S. Pat. No. 6,479,974 proposes to adjust switching activities in the workload sub-circuits at run time such as to balance their supply currents and, hence, also the voltage drops across them. The patent even suggests the duplication of logic circuitry to provide for sufficient headroom for activity adjustments.